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Título del libro: 11th Ieee Workshop On Control And Modeling For Power Electronics, Compel 2008
Título del capítulo: A DVS system based on the trade-off between energy savings and execution time

Autores UNAM:
OSCAR PROSPERO GARCIA;
Autores externos:

Idioma:
Inglés
Año de publicación:
2008
Palabras clave:

Commerce; Digital circuits; Digital integrated circuits; Electric power utilization; Petroleum products; Power electronics; Technical presentations; Clock frequencies; Commercial products; Dvs algorithms; DVS systems; Dynamic powers; Dynamic voltage scaling; Energy savings; Execution times; Hitachi; Maximum values; Power consumptions; Power savings; Power supplies; Slew rates; Supply voltages; System performances; Transmeta; Workload estimations; Voltage stabilizing circuits


Resumen:

DVS (Dynamic Voltage Scaling) is a technique used for reducing the power consumption of digital circuits. The power consumed by these circuits has a main component (dynamic power) that is proportional to the square of the supply voltage. Additionally, for every supply voltage, there is a maximum value of the clock frequency. The advantage of using DVS is that the supply voltage (and hence clock frequency) can be adjusted depending on the specific needs during execution. The DVS concept has been used in some commercial products like Transmeta's Crusoe [1], Intel Speed Step [2], AMD K6 [3], Hitachi SH4 [4], etc. This paper presents results obtained by using a DVS algorithm based on the workload estimation and trade-off between the execution time and power savings. It is discussed about influence of the power supply's slew rate, algorithms influence on the system performance and problems to estimate the processors workload. The DVS system is realized on Intel's PXA255 platform and energy savings have been calculated by measuring directly voltages and currents on the platform. ©2008 IEEE.


Entidades citadas de la UNAM: